Cypress Semiconductor /psoc63 /HSIOM /PRT[11] /PORT_SEL0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PORT_SEL0

IO0_SEL=GPIO

Description

Port selection 0

Fields

IO0_SEL	Selects connection for IO pin 0 route. 0 (GPIO): GPIO controls ‘out’ 1 (GPIO_DSI): GPIO controls ‘out’, DSI controls ‘output enable’ 2 (DSI_DSI): DSI controls ‘out’ and ‘output enable’ 3 (DSI_GPIO): DSI controls ‘out’, GPIO controls ‘output enable’ 4 (AMUXA): Analog mux bus A 5 (AMUXB): Analog mux bus B 6 (AMUXA_DSI): Analog mux bus A, DSI control 7 (AMUXB_DSI): Analog mux bus B, DSI control 8 (ACT_0): Active functionality 0 9 (ACT_1): Active functionality 1 10 (ACT_2): Active functionality 2 11 (ACT_3): Active functionality 3 12 (DS_0): DeepSleep functionality 0 13 (DS_1): DeepSleep functionality 1 14 (DS_2): DeepSleep functionality 2 15 (DS_3): DeepSleep functionality 3 16 (ACT_4): Active functionality 4 17 (ACT_5): Active functionality 5 18 (ACT_6): Active functionality 6 19 (ACT_7): Active functionality 7 20 (ACT_8): Active functionality 8 21 (ACT_9): Active functionality 9 22 (ACT_10): Active functionality 10 23 (ACT_11): Active functionality 11 24 (ACT_12): Active functionality 12 25 (ACT_13): Active functionality 13 26 (ACT_14): Active functionality 14 27 (ACT_15): Active functionality 15 28 (DS_4): DeepSleep functionality 4 29 (DS_5): DeepSleep functionality 5 30 (DS_6): DeepSleep functionality 6 31 (DS_7): DeepSleep functionality 7
IO1_SEL	Selects connection for IO pin 1 route.
IO2_SEL	Selects connection for IO pin 2 route.
IO3_SEL	Selects connection for IO pin 3 route.

Links

() ()